Laboratory 5/6 - CAPC Processor (Step 1)

In this experiment, we are to wire machine instruction LDG, load G register in the Skeletal Processor 2 created in the Laboratory 3/4.

(1) Load the following Skeletal Processor 2 created in Lab3/4.

(2) We will wire LDG, load G register, instruction as follows.

(2a)First choose a 16 bit register with two control lines, SEND and LOAD, from your own library. attach it to the right side of the design sheet.

(2b)At the subcycle 3, the machine operation "IR[0..11] -> MAR" and "mem -> MBR" will be wired.

(2b1) Select a AND2 gate from the tool box and wire it with the subcycle 3 line and LDG line (line 6) of the macine instruction decoder, MACH. The output line of this AND gate, LDG-C3, is to be connected with SEND line of the IR buffer, IR[0..11], and 4 bit ZERO register.

(2b2) With a delay (3 time unit), connect further the output line of LDG-3C to LOAD port of MAR, memory address register. With additional delay (3 time unit), extend the output line further and connect to LOAD port of MBR, memory buffer register.

(2c)At the subcycle 4, the machine operation "MBR -> Greg" will be wired.

(2c1) Select a AND2 gate from the tool box and wire it with the subcycle 4 line and LDG line (line 6) of the macine instruction decoder, MACH. The output line of this AND gate, LDG-C4, is to be connected with SEND port of the MBR.

(2c2) With a delay (3 time unit), connect further the output line of LDG-3C to LOAD port of Greg.

(3) Test the wiring of LDG.

(3a) Prepare the following machine instructions in NOTEPAD and store it in "LAB6.HEX".

0 FFFF
nop
1 6004
ldg [004]
2 0000
hlt
3 0000
hlt
4 BBBB
data "BBBB"

(3b) Create new PROM chip based on the program "LAB6.HEX".
(3c) Replace the PROM by new chip (3b) and start CAPC processor. Observe that the datum "BBBB" in the memory located at "004" is copied into Greg register.

(4) Submit your successful CAPC processor 1 design (relevant .CCT files) to Dr. Hasegawa by Sunday, March 7, 10:00pm.