Laboratory 8 - CAPC Processor (Step 3)

In this experiment, we are to wire the machine instruction SDG, send G register, in the CAPC Processor (Step 2) design created in the Laboratory 7.

(1) Load the following CAPC Processor 2 created in Lab6/7.

(2) Wire the output line of SDG (Q7 port of MACH, Machine Instruction Decoder) and SC3, Subcycle 3 of the Clock, to the Send line of Zero and Buffer12 (of IR register).

(3) Extend the output line of SDG (Q7 port of MACH, Machine Instruction Decoder) and SC3, Subcycle 3 of the Clock, to the Load line of MAR, Memory Address Register.

(4) Wire the output line of SDG (Q7 port of MACH, Machine Instruction Decoder) and SC4, Subcycle 4 of the Clock, to the Send line of Greg, G register.

(5) Extend the output line of SDG (Q7 port of MACH, Machine Instruction Decoder) and SC4, Subcycle 4 of the Clock, to the Load line of MBR2, Memory (Input) Buffer Register. Extend further the line to the Send line of MBR2 and then to NOT(/WE) line of the RAM.

(6) Store manually the following test program in RAM.

0 FFFF
nop
1 6100
ldg [100]
2 7101
sdg [101]
3 0000
hlt
100 ABCD
data "ABCD"
101 0000
data "0000"

The datum "ABCD" will be stored at the location 101 in the RAM after the successful run.

(8) Submit your successful CAPC processor 3 design (relevant .CCT files) to Dr. Hasegawa by Sunday, March 21, 11:00pm.