Laboratory 9 - CAPC Processor (Step 4)

In this experiment, we are to design/build an ALU, Arithmetic and Logic Unit, and wire the machine instruction ADD, Add G register, one of the arithmetic instructions of the CAPC Processor. The circuits will be attached to the processor created in the Laboratory 8.

(1) Create an ALU step by step by following ALU Design instructions. The ALU unit is composed of the combinational circuit ALU, two 16 bit input registers Xreg, Yreg and Z with a separate 16 bit Buffer Zb (mainly for debugging purposes).

(2)Wire the machine instruction ADD as follows:

(2a) At the subcycle 3, SC3, the 16 bit datum in the memory at the address pointed by the operand is read to MBR, Memory Buffer Register. It is exactly same as the circuit for LDG&SC3.

(2b) At the subcycle 4, SC4, the content of MBR is to be copied into Xreg register in the ALU. The wiring for the SEND line of MBR is exactly same as one for the first part of LDG&SC4.

(2c) At the subcycle 5, SC5, the content of Greg is to be copied into Yreg register in the ALU.

(2d) At the subcycle 6, SC6, the result of ADD operation is to be stored into Z register in the ALU.

(2e) At the subcycle 7, SC7, the content of Z register is to be copied in the Greg, completing the ADD operation.

(3) In order to check your wiring of ALU and the machine instruction ADD, store manually the following test program in RAM. The program also rechecks the circuits of the previous CAPC processor.

0 FFFF
nop
1 6100
ldg [100]
2 7200
sdg [200]
3 6101
ldg [101]
4 7201
sdg [201]
5 1200
add [200]
6 7202
sdg [202]
7 0000
hlt
100 ABCD
data "ABCD"
101 1234
data "1234"
200 0000
data "0000"
201 0000
data "0000"
202 0000
data "0000"

The data "ABCD", "1234", and "BE01" will be stored at the location 200,201 and 202 respectively in the RAM after the successful run.

(8) Submit your successful CAPC processor 4 design (relevant .CCT files) to Dr. Hasegawa by Sunday, March 28, 11:00pm.