CAPC Processor Design in LogicWorks 4

The LogicWork 4 is an interactive circuit design software, cost-effective tool, developed by Capilano Computing Systems Ltd here in Vancouver, BC. In this course, we will design and build a 16 bit processor step by step in the LogicWorks 4 system environment. First we will start with general overview of a 16 bit processor, CAPC1, and its description.

(1) CAPC1 is a sequential processor with main memory (RAM) of size 4,096 words, 16 bits per word.
(2) It is controlled/driven by a clock, generating Fetch/Execute cycle in 8 subcycles.
(3) There is only one 16 bit Bus for both data, 16 bits, and addresses, 12 bits.
(4) Each word, when it is used as a machine instruction, contains a 4 bit OP code (bits 12,13,14, and 15) and an Operand, an address (bits 0 to 11).
(5) ALU unit consists of two input registers, X and Y, and one output register Z. It is capable of computing ADD (Z=X+Y), AND, OR, XOR, and NEG (Z=-X).
(6) There are two 16 bit registers; instruction register IR, and general purpose register Greg. IR is the main register to decode and execute a machine instruction.
(7) The 12 bit memory address register MAR is used to point the location in the main memory. The 16 bit register MBR, memory buffer register, is used to interface with the datum into/from the main memory.
(8) There are 16 Machine Instructions (OP codes):
OP code Operand Instruction Description
0000 xxxxxxxxxxxx HLT Halt the clock signal.
Operand is ignored.
0001 xxxxxxxxxxxx ADD Add Greg to the 16 bit datum in
the memory pointed by Operand.
Store the result to Greg.
0010 xxxxxxxxxxxx XOR Bit by bit, XOR Greg to the 16 bit datum
in the memory pointed by Operand.
Store the result to Greg.
0011 xxxxxxxxxxxx OR OR Greg to the 16 bit datum in
the memory pointed by Operand.
Store the result to Greg.
0100 xxxxxxxxxxxx AND AND Greg to the 16 bit datum in
the memory pointed by Operand.
Store the result to Greg.
0101 xxxxxxxxxxxx NOT NOT the contents of Greg.
Store the result to Greg.
Ignore the Operand
0110 xxxxxxxxxxxx LDG Load Greg the 16 bit content of
the memory pointed by Operand.
0111 xxxxxxxxxxxx SDG Send(Copy) the contents of Greg to
the memory pointed by Operand.
1000 xxxxxxxxxxxx SRJ Jump to the memory pointed by Operand.
Store the return address (PC+1) to Greg.
1001 xxxxxxxxxxxx JMI Jump to the memory pointed by Operand
if the bit 15 of Greg is 1.
1010 xxxxxxxxxxxx JMP Jump to the memory pointed by Operand.
1011 xxxxxxxxxxxx INJ Jump (indirectly) to the location given
in the memory pointed by Operand.
1100 xxxxxxxxxxxx INT Software interrupt.
Interrupt Number is xxxxxxxxxxxx.
1101 xxxxxxxxxxxx ROL Rotate 1 bit of Greg to the left.
Fill in 0 to the right most bit.
Ignore Operand.
1110 xxxxxxxxxxxx SHR Shift 1 bit of Greg to the right.
Keep the highest bit intact.
Ignore Operand.
1111 xxxxxxxxxxxx NOP No action is generated.

CAPC1 Processor

The following schematic is the entire view of CAPC1 processor designed in LogicWorks 4. It is placed in a rectangular frame for debugging purpose (slide easily left and right in a window). Click a part of the schematic to have a closer look. Refer to each section for more details.

clock unit memory unit unit ONE clock unit ALU unit IR unit decoder unit