Introduction to CAPC Processor Project 2005

1. Summary

CAPC Processor is a 16 bit processor with main memory (RAM) of size 4,096 words, 16 bits per word. It was designed/built in LogicWorks4 for COMP212 Course (Computer Design and Architecture II) at Capilano College in the Spring2002 term. The CAPC Processor project (design/build the Processor) has been the major part of this course.

2. History

The design of the first CAPC processor was based on a standard Von Neuman machine. I named this particular model Foster machine in honour of Caxton Foster, University of Massachusetts. His text book on the subject was popular back in the late 1970s and 1980s. His clear, simple and elegant design of a processor, machine BLUE, was a joy to study (and teach) in Computer Design and Architecture course. I first taught the Foster Machine in the Computer Architecture course at Lakehead University, Thunder Bay, Ontario, Canada. At that time, students had to draw the schematics by hand or some mechanical drawing device. Then came an iteractive circuit design software LogicWorks3 in 1996. Some of the students soon started using LW3 for their 8-bit Processor Design projects.

The Computing Science Department at Capilano College had been using LogicWorks4 for the circuit design in COMP212. In the 2002Spring term, I designed/built a 16 bit processor a la Foster by introducing a main control unit in LW4. The processor CAPC was named after our Capilano College. Sometimes unexpected behaviour of our circuits and possible memory limitations of PCs in case of dealing with RAM made the students including myself ran off for cover blaming the most obvious target - LW4. However, somehow we managed to create a 16 bit working order CAPC processor. The achievement is also a tribute to the durable nature of LogicWorks4 system. The report is included in the Web reports - CAPC Processor Presentation 2002. In the 2003Spring term, I tried to simplify the design and complete the Web text book - Build your own Processor in LW4.

3. 2004 Spring Term

I tried to make my design simpler and decided to wire the complete "Fetch Cycle" without using the ALU by combining PC with a simple adder, PlusOne, for the arithmetic operation "PC <- PC+1". Refer to CAPC Processor Project Presentation 2004.

4. 2005 Spring Term

The Laboratory experiments sequence to build the CAPC Processor, introduced in 2004 Spring Term, is definitely an improvement. One of my students, Scott Peerenboon, has finished the design and built CAPC Processor in a month !! This is a remarkable achievement.

Dr. Minoru Hasegawa
Department of Computing Science
Capilano College
North Vancouver, BC, Canada