COMP212 Computer Architecture and Organization Project - MAC1

DescriptionNote
Introduction Tanenbaum's Machine MAC1 was introduced as an example of a modern multilevel computer in his text, Structured Computer Organization, Prentice-Hall. His precise description of this two level machine makes it possible to design and build a working model of MAC1 in LogicWorks4(/5). MAC1 requires much resources, perhaps beyond the scope of LogicWorks4(/5). However, LW4(/5)'s naming function provides a way to solve some of the problems due to lack of resources.
Step1
Design of Level0
(Base) Machine
You will be surprised to realize that MAC1's Level0 machine is an enhanced skeletal machine, called HASB which is the engine of your CAPC processor designed/built in LogicWorks4(/5).

Step1A Encode the microprogram of Tanenbaum's level0 machine into corresponding 32-bit machine codes.
Step1B Create a 8x32 ROM with 79 lines of machine codes in Step1A.
Step1C Attach the ROM built in Step1B to your skeletal machine.
Step1D Use naming_device tool and create a chip, called HASB6 in the following schematic, from the device created in Step1A-C.

Step2
Design of Registers
and Buses
MAC1 has 16 registers,namely, PC,AC,SP,IR,TIR,0,+1,-1,AMASK,SMASK,A,B,C,D,E, and F. These registers are connected to 16-bit output A bus and B bus, and input C bus. Unfortunately, you will find setting up these devices in a schematic causes problems due to lack of resources. My recommendation is as follows:

Step2A Create a 8 register array, PC,AC,SP,IR,TIR,A,B,and C.
Step2B Create a 5 constant array, 0,+1,-1,AMASK,and SMASK.
Step2C Combine them and create 16 (3 not used) register array with outputs conneted with A bus and B bus, their destination being A latch and B latch respectively. Use C bus for an input bus to the 8 register array.
Step2D Use naming_device tool and create a chip, called ARRAY16 in the following schematic, from the device created in Step2A-C.
Step2E Change register numbers in machine codes in Step1B. Recreate HASB6 in Step1.

Step3
Design of ALU
and Memory
Design of ALU with a shifter and 4K Memory is the same as in CAPC processor. You will need a multiplexter, Amux, to deal with 16 bit input from A latch or MBR to the port A of ALU.

Step3A Create an ALU with a shifter as in CAPC processor.
Step3B Create a RAM with a sample machine program in MAC1 machine language to test MAC1. Start with a simple instruction such as "LODD 100" (0100H).
Step3C Combine HASB6 in Step1 and ARRAY16 in Step2 with above ALU and 4K memory as in the following schematic.
Step2D Experiment with the timing described in Tanenbaum's text and the micro sequencing logic from Level1 structure to Level0 machine as in the following schematic (under ALU16 at the bottom).